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APAC Algo Trading Low Latency C++ Developer
senior · Technology / Software Development
Key responsibilities
Join a high-performance team building ultra-low latency trading systems where nanoseconds matter. You’ll design and implement a trading rules engine for real-time controls using a hybrid of FPGA hardware and high-performance C++, enabling deterministic execution and rapid interaction with the markets.• Design and implement real-time trading rules and risk checks using FPGA (Verilog/VHDL) or C++.
• Architect cycle-accurate FPGA designs and high-speed network interfaces (10/25/40/100GbE, RoCEv2) is preferred.
• Build simulation and verification frameworks for FPGA reliability.
• Drive full FPGA design flow (synthesis, place & route, timing closure).
• Interface C++ applications with FPGA hardware for real-time orchestration.
• Implement lock-free data structures and concurrency control in Linux.
• Build low-latency network apps using kernel bypass (e.g., Rivermax).
• Analyze system performance and resolve latency bottlenecks.
• Collaborate with global IT, Quants, and Traders across asset classes.
• Provide Level 3 support for production systems.
Join us
At UBS, we know that it's our people, with their diverse skills, experiences and backgrounds, who drive our ongoing success. We’re dedicated to our craft and passionate about putting our people first, with new challenges, a supportive team, opportunities to grow and flexible working options when possible. Our inclusive culture brings out the best in our employees, wherever they are on their career journey. And we use artificial intelligence (AI) to work smarter and more efficiently. We also recognize that great work is never done alone. That’s why collaboration is at the heart of everything we do. Because together, we’re more than ourselves.We’re committed to disability inclusion and if you need reasonable accommodation/adjustments throughout our recruitment process, you can always contact us.
Contact Details
UBS Business Solutions SAUBS Recruiting
Disclaimer / Policy statements
UBS is an Equal Opportunity Employer. We respect and seek to empower each individual and support the diverse cultures, perspectives, skills and experiences within our workforce.The team
You’ll be part of the Algorithmic Trading Team based out of Shanghai within the Execution Services, delivering latency-sensitive infrastructure for Algorithmic Execution, Smart Order Routing, Internalization, and Real-time Controls across global markets.Your skills and experience
• 7+ years in FPGA (Verilog/VHDL) or low-latency C++ development.• Expert in C++17/20/23, Linux system programming, concurrency.
• Deep knowledge of FPGA toolchains (Vivado, Quartus), timing closure.
• Experience with high-speed networking and hardware acceleration.
• Strong background in shared memory IPC and lock-free systems.
• Familiarity with market microstructure and trading protocols (FIX, ITCH) is a plus.
• Degree in Computer Science, Electrical Engineering, or related field.
• Performance-obsessed and precision-driven.
• A hands-on engineer who thrives in fast-paced environments.
• A collaborative communicator.
• Self-motivated with a passion for solving complex technical challenges.
About us
UBS is a leading and truly global wealth manager and the leading universal bank in Switzerland. We also provide diversified asset management solutions and focused investment banking capabilities. Headquartered in Zurich, Switzerland, UBS is present in more than 50 markets around the globe.We know that great work is never done alone. That’s why we place collaboration at the heart of everything we do. Because together, we’re more than ourselves. Want to find out more? Visit ubs.com/careers.